题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				       clk 		    ,   
	input 				       rst_n		,
	input				       valid_in   	,
	input	     [7:0]		   data_in	    ,
 
 	output	 reg			   valid_out    ,
	output   reg [15:0]	       data_out
);

reg [7:0] data_in_reg     ; //给输入数据打一拍寄存 ，再加上拼接就可以输出16bit
reg [2:0] cnt             ;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
        cnt <=  'd0       ;
	else if(cnt == 'd1 && valid_in == 1'b1)
	    cnt <=  'd0       ;
	else if(valid_in == 1'b1)
	    cnt <= cnt + 1'b1 ;
end

// 打一拍寄存前一个周期数据
always@(posedge clk)begin
	data_in_reg <= data_in ;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 1'b0   ;
		data_out  <=  'd0   ;   
	end
	else if( cnt == 'd1 && valid_in == 1'b1)begin
		valid_out <= 1'b1                  ;
		data_out  <=  {data_in_reg,data_in};
	end
	else begin
		valid_out <= 1'b0                  ;
		data_out  <= data_out              ;
	end
end


endmodule