题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,

	output reg data
);

reg [2:0]cnt;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    cnt <= 3'b0;
	else if (cnt == 3'd5)
	    cnt <= 3'b0;
	else 
	    cnt <= cnt + 1'b1;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data <= 1'b0;
	else 
	    case (cnt)
		    3'd0 : data <= 1'b0;
			3'd1 : data <= 1'b0;
			3'd2 : data <= 1'b1;
			3'd3 : data <= 1'b0;
			3'd4 : data <= 1'b1;
			3'd5 : data <= 1'b1;
			default : data <= 1'b0;
		endcase

endmodule