题解 | #不重叠序列检测#（两种方法 题目没错）

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output wire match,      //状态机方法改为reg型
	output wire not_match  //状态机方法改为reg型
	);

/*
   reg [7:0] cur_state;
   reg [7:0] nex_state;

   parameter  IDLE   =  8'b00_000_001 ,
              S0     =  8'b00_000_010 ,
			  S1     =  8'b00_000_100 ,
			  S2     =  8'b00_001_000 ,
			  S3     =  8'b00_010_000 ,
              S4     =  8'b00_100_000 ,
              S5     =  8'b01_000_000 ,
              error  =  8'b10_000_000 ;
              
    
     reg [2:0] cnt ;
   always@(posedge clk or negedge rst_n)begin
       if(!rst_n)
           cnt <= 'd0;
       else if(cnt == 'd5)
           cnt <= 'd0;
       else 
           cnt <= cnt + 1'b1 ; 
   end
   
   //////三段式状态机/////////////////////////////
   always@(posedge clk or negedge rst_n)begin
       if(!rst_n)
           cur_state <= IDLE      ;
       else 
           cur_state <= nex_state ; 
   end
   
   always@(*)begin
      case(cur_state)
          IDLE: begin
              if(data == 1'b0)
                  nex_state <= S0    ;
              else
                  nex_state <= error ;
          end
          S0: begin
              if(data == 1'b1)
                  nex_state <= S1    ;
              else
                  nex_state <= error ;
          end
          S1: begin
              if(data == 1'b1)
                  nex_state <= S2    ;
              else
                  nex_state <= error ;
          end
          S2: begin
              if(data == 1'b1)
                  nex_state <= S3    ;
              else
                  nex_state <= error ;
          end
          S3: begin
              if(data == 1'b0)
                  nex_state <= S4    ;
              else
                  nex_state <= error ;
          end
          S4: begin
              if(data == 1'b0)
                  nex_state <= S5    ;
              else
                  nex_state <= error ;
          end
          S5: begin
              if(data == 1'b0)
                  nex_state <= S0    ;
              else
                  nex_state <= error ;
          end
          error: begin
              if(cnt == 'd5)
                  nex_state <= IDLE    ;
              else
                  nex_state <= error   ;
          end
          
          default: nex_state <= IDLE    ;
      endcase
   end
   
   always@(posedge clk or negedge rst_n)begin
       if(!rst_n)begin
           match     <= 1'b0;
           not_match <= 1'b0;
       end
       else if(cnt == 'd5)begin
           if(nex_state == S5)begin
               match     <= 1'b1;
               not_match <= 1'b0;
           end
           else begin
               match     <= 1'b0;
               not_match <= 1'b1;
           end 
       end
       else begin
           match     <= 1'b0;
           not_match <= 1'b0;    
       end
   end
 */  
   
  
   

//题目没有错 移位实现 要考虑时序
   reg [5:0] reg_num;
   reg [2:0] cnt    ;
  //移位 + 拼接实现寄存
  always@(posedge clk or negedge rst_n)begin
     if(!rst_n)
         reg_num <= 'd0;
     else 
         reg_num <= {reg_num[4:0], data};
  end
  
  //计数器
  always@(posedge clk or negedge rst_n)begin
     if(!rst_n)
         cnt <= 'd0;
     else if(cnt == 'd6)
         cnt <= 'd1;
     else 
         cnt <= cnt + 1'b1;
  end
/*  
  always@(posedge clk or negedge rst_n)begin
      if(!rst_n)begin
          match     <= 1'b0;
          not_match <= 1'b0;
      end
      else if(cnt == 'd6)begin
          if(reg_num == 6'b011100)begin
              match     <= 1'b1;
              not_match <= 1'b0; 
          end              
          else begin
              match     <= 1'b0;
              not_match <= 1'b1;  
          end  
      end
      else begin
          match     <= 1'b0;
          not_match <= 1'b0;
      end 
  end
 */
  assign  match     = (cnt == 'd6 & reg_num == 6'b011100)?1'b1:1'b0;
  assign  not_match = (cnt == 'd6 & reg_num != 6'b011100)?1'b1:1'b0;
  
endmodule