题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);
	
/*
两级寄存来做边缘检测的思路是对的 测试用例就是过不了 
	reg [1:0] a_reg;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			a_reg <= 2'b00;
		end
		else begin
			a_reg[0] <= a        ;
		    a_reg[1] <= a_reg[0] ;
		end
	end


    assign rise = (a_reg == 2'b01)? 1'b1 : 1'b0 ;
	assign down = (a_reg == 2'b10)? 1'b1 : 1'b0 ;

*/
reg  a_reg;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			a_reg <= 1'b0;
		end
		else begin
			a_reg <= a        ;
		end
	end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		rise <= 1'b0;
		down <= 1'b0;
	end
	else begin
		if({a,a_reg}== 2'b10)begin
			rise <= 1'b1;
			down <= 1'b0;
		end
		else if({a,a_reg}== 2'b01)begin
			rise <= 1'b0;
			down <= 1'b1;
		end
	    else begin
			rise <= 1'b0;
			down <= 1'b0; 
		end
	end
end

endmodule