题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg [1:0] cur_state;
reg [1:0] nex_state;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        cur_state <= 2'b00;
    else
        cur_state <= nex_state;
end

always@(*)begin
    case(cur_state)
        2'b00:   nex_state = (C == 1)? 2'b01 : 2'b00;
        2'b01:   nex_state = (C == 1)? 2'b01 : 2'b11;
        2'b10:   nex_state = (C == 1)? 2'b10 : 2'b00;
        2'b11:   nex_state = (C == 1)? 2'b10 : 2'b11;
        default: nex_state = 2'b00;
    endcase
end

assign  Y =  ((cur_state == 2'b11) | (cur_state == 2'b10 & C == 1)) ? 1'b1 : 1'b0;

endmodule