题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

reg cnt;
reg [7:0]data_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    cnt <= 1'b0;
	else if ( valid_in == 1'b1 )
	    cnt <= cnt + 1'b1;
	else 
	   cnt <= cnt;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_reg <= 8'b0;
	else if (valid_in == 1'b1 && cnt == 1'b0)
	   data_reg <= data_in;
	else 
	   data_reg <= data_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    valid_out <= 1'b0;
	else if (valid_in == 1'b1 && cnt == 1'b1)
	    valid_out <= 1'b1;
	else 
	    valid_out <= 1'b0;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    data_out <= 15'b0;
	else if (valid_in == 1'b1 && cnt == 1'b1)
	    data_out <= {data_reg,data_in};
	else 
	    data_out <= data_out;

endmodule