题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);

reg [5:0] data;
reg data_out;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data <= 6'b010000;
		data_b <= 'd0;
		valid_b <= 'd0;
		ready_a <= 0;
		data_out <= 'd0;
	end
	else begin
		ready_a <= 1;
		if(valid_a)begin
			data <= (valid_b)?{data_a,5'b01000} : {data_a,data[5:1]};
			data_out<=(valid_b)? 0: data[0];
			if(data_out) begin
			valid_b <= 'd1;
			data_b <= {data_a,data[5:1]};
			end
			else 
			valid_b <= 0;	
		end
		else
		valid_b <= 0;
	end
end


endmodule

休息一下。。