题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg    [3:0]   aloc, bloc, cloc, dloc;

reg             validout_reg;
reg     [4:0]   out_reg     ;


always @(posedge clk or negedge rst) begin
if(~rst) begin
    validout_reg    <= 1'b0;
    out_reg         <= 5'b0;
end else begin 
    case(sel)
    2'b01:  begin
        validout_reg    <= 1'b1;
        out_reg         <= aloc + bloc;
    end
    2'b10:  begin
        validout_reg    <= 1'b1;
        out_reg         <= aloc + cloc;
    end
    2'b11:  begin
        validout_reg    <= 1'b1;
        out_reg         <= aloc + dloc;
    end    
    default:begin
        validout_reg    <= 1'b0;
        out_reg         <= 5'b0;
        aloc            <= d[3:0];
        bloc            <= d[7:4];
        cloc            <= d[11:8];
        dloc            <= d[15:12];
        
    end
    endcase
end
end

assign out = out_reg;
assign validout = validout_reg;

//*************code***********//
endmodule