题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output  reg down
);

reg [1:0] r_a;
//wire pos_a , neg_a;

always@(posedge clk,negedge rst_n)
	begin
		if(rst_n==1'b0) r_a <= 2'b00;
		else r_a <= {r_a[0],a};
	end
//以下两段代码无法处理初始阶段不定态r_a==x和中间a=x
/*
always@(posedge clk)
	begin
		if(rst_n==1'b0) 
			begin
				rise <= 1'b0;
				down <= 1'b0;
			end
		else 
			begin
				rise <= ~r_a[1] && r_a[0];
				down <= r_a[1] && ~r_a[0];
			end;
	end
*/

/*
assign rise = (~r_a[1] & r_a[0]) ? 1:0;
assign down = (r_a[1] & ~r_a[0]) ? 1:0;
*/

//异步复位能够保证最初时刻没有不定，但时序逻辑输出晚了一拍
/*
always@(posedge clk,negedge rst_n)
	begin
		if(rst_n==1'b0) 
			begin
				rise <= 1'b0;
				down <= 1'b0;
			end
		else if((r_a[1] | r_a[0]) == 1'b1)
			begin
				rise <= ~r_a[1] & r_a[0];
				down <= r_a[1] & ~r_a[0];
			end
		else 
			begin
				rise <= 1'b0;
				down <= 1'b0;
			end	
	end
*/

//rise 有不定态
/*
always@(r_a)
	begin
		if((r_a[1] | r_a[0]) == 1'b1)
			begin
				rise = ~r_a[1] & r_a[0];
				down = r_a[1] & ~r_a[0];
			end
		else 
			begin
				rise = 1'b0;
				down = 1'b0;
			end	
	end
*/

always@(r_a)
	begin
		if((r_a[1] | r_a[0]) == 1'b1)
			begin
				if(~r_a[1] & r_a[0] == 1'b1) rise = 1'b1;
				else if(r_a[1] & ~r_a[0] == 1'b1)   down = 1'b1;
				else 
					begin
						rise = 1'b0;
						down = 1'b0;
					end	
			end
		else 
			begin
				rise = 1'b0;
				down = 1'b0;
			end	
	end
endmodule