题解 | #全加器#

`timescale 1ns/1ns

module add_half(
   input                A   ,
   input                B   ,
 
   output	wire        S   ,
   output   wire        C   
);

assign S = A ^ B;
assign C = A & B;
endmodule

/***************************************************************/
module add_full(
   input                A   ,
   input                B   ,
   input                Ci  , 

   output	wire        S   ,
   output   wire        Co   
);
   wire S_h;
   wire C_h,C2;

   add_half inst_half0(
    .A (A)  ,
    .B (B)  ,
    
    .S (S_h) ,
    .C (C_h)  
    );

    add_half inst_half1(
    .A (S_h)  ,
    .B (Ci)  ,
    
    .S (S) ,
    .C (C2)  
    );

    assign Co = C_h | C2;

endmodule