题解 | #根据状态转移写状态机-二段式#

`timescale 1ns/1ns

module fsm2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);

//*************code***********//
parameter s0 = 3'd0,
		  s1 = 3'd1,
		  s2 = 3'd2,
		  s3 = 3'd3,
		  s4 = 3'd5;

reg [2:0] cur_st,nxt_st;

always @(posedge clk or negedge rst)begin
	if(rst == 1'b0)
		cur_st <= s0;
	else
		cur_st <= nxt_st;
end

always @(*)(1444584) begin
		case(cur_st)
			s0:begin
				if(data == 1'b1)begin
					nxt_st = s1;
					flag = 1'b0;
				end
				else begin
					nxt_st = s0;
					flag = 1'b0;
				end
			end
			s1:begin
				if(data == 1'b1)begin
					nxt_st = s2;
					flag = 1'b0;
				end
				else begin
					nxt_st = s1;
					flag = 1'b0;
				end
			end
			s2:begin
				if(data == 1'b1)begin
					nxt_st = s3;
					flag = 1'b0;
				end
				else begin	
					nxt_st = s2;
					flag = 1'b0;
				end
			end
			s3:begin
				if(data == 1'b1)begin
					nxt_st = s4;
					flag = 1'b0;
				end
				else begin
					nxt_st = s3;
					flag = 1'b0;
				end
			end
			s4:begin
				if(data == 1'b1)begin
					nxt_st = s1;
					flag = 1'b1;
				end
				else begin
					nxt_st = s0;
					flag = 1'b1;
				end
			end

			default: begin
				nxt_st = s0;
				flag = 1'b0;
			end
		endcase
	end

//*************code***********//
endmodule