题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
	reg [2:0] cur_st,nxt_st;

	parameter s0 = 3'd0,
			  s1 = 3'd1,
			  s2 = 3'd2,
			  s3 = 3'd3,
			  s4 = 3'd4;
	
	always @(posedge clk or negedge rst)begin
		if(rst == 1'b0)
			cur_st <= 3'd0;
		else
			cur_st <= nxt_st;
	end

	always @(*)begin
		case(cur_st)
			s0:begin
				if(data == 1'b1)
					nxt_st = s1;
				else
					nxt_st = s0;
			end
			s1:begin
				if(data == 1'b0)
					nxt_st = s2;
				else
					nxt_st = s1;
			end
			s2:begin
				if(data == 1'b1)
					nxt_st = s3;
				else
					nxt_st = s0;
			end
			s3:begin
				if(data == 1'b1)
					nxt_st = s4;
				else
					nxt_st = s2;
			end
			s4:begin
				if(data == 1'b1)
					nxt_st = s0;
				else
					nxt_st = s2;
			end
			default: nxt_st = s0;
		endcase
	end

	always @(posedge clk or negedge rst) begin
		if(rst == 1'b0)
			flag <= 1'b0;
		else if(cur_st == s4)
		 	flag <= 1'b1;
		else
			flag <= 1'b0;
	end

//*************code***********//
endmodule