题解 | #状态机-重叠序列检测#
状态机-重叠序列检测
https://www.nowcoder.com/practice/10be91c03f5a412cb26f67dbd24020a9
写成了米利机，为了和答案对上，最后增加了一级寄存器输出。
`timescale 1ns/1ns
module sequence_test2(
input wire clk ,
input wire rst ,
input wire data ,
output reg flag
);
//*************code***********//
parameter IDEL=0, S0=1, S1=2, S2=3;
reg [1:0] cstate, nstate;
always@(posedge clk or negedge rst) begin
if(!rst) begin
cstate <= IDEL;
end
else begin
cstate <= nstate;
end
end
always@(*) begin
case(cstate)
IDEL: nstate = data?S0:IDEL;
S0: nstate = data?S0:S1;
S1: nstate = data?S2:IDEL;
S2: nstate = data?S0:S1;
default:nstate = IDEL;
endcase
end
reg flag_reg;
always@(posedge clk or negedge rst) begin
if(!rst) begin
{flag,flag_reg} <= 2'b00;
end
else begin
{flag,flag_reg} <= {flag_reg,(cstate==S2) & data};
end
end
//*************code***********//
endmodule
