题解 | #自动售卖机#

`timescale 1ns/1ns

module sale(input clk,
            input rst_n,
            input sel,
            input [1:0] din,
            output reg [1:0] drinks_out,
            output    reg change_out);
    parameter idle = 3'b000;
    parameter s05  = 3'b001;
    parameter s10  = 3'b010;
    parameter s15  = 3'b100;
    reg [2:0] cs,ns;
    always@(posedge clk or negedge rst_n)
        cs <= ~rst_n?idle:ns;
    always@(*) begin
        ns = idle;
        case(cs)
            idle: ns    = din == 0?idle:din == 1?s05:din == 2?s10:idle;
            s05:  ns    = sel?(din == 0?s05:din == 1?s10:din == 2?s15:idle):(din == 0?idle:din == 1?s05:din == 2?s10:idle);
            s10:  ns    = din == 0?idle:din == 1?s05:din == 2?s10:idle;
            s15:  ns    = din == 0?idle:din == 1?s05:din == 2?s10:idle;
            default: ns = idle;
        endcase
    end
    always@(posedge clk or negedge rst_n) begin
        if (!rst_n)
            drinks_out <= 0;
        else
            drinks_out <= sel?((ns == s10 || ns == s15)?2:0):((ns == s05 || ns == s10 | cs == s15)?1:0);
    end
    always@(posedge clk or negedge rst_n) begin
        if (!rst_n)
            change_out <= 0;
        else
            change_out <= sel?((ns == s15)?1:0):((ns == s10 || ns == s15)?1:0);
    end
endmodule