题解 | #序列发生器#
此为状态机写法，三段式状态机
module sequence_generator(
input clk,
input rst_n,
output reg data
);
reg [2:0] state,nstate;
parameter s0=3'd0,s1=3'd1,s2=3'd2,s3=3'd3,s4=3'd4,s5=3'd5;//定义6个状态
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
state<=s0;
else
state<=nstate;
end
always @(*)//状态转移
begin
if(!rst_n)
nstate<=s0;
else
begin
case(state)//因为是序列发生器，所以状态直接转移不需要条件
s0:nstate<=s1;
s1:nstate<=s2;
s2:nstate<=s3;
s3:nstate<=s4;
s4:nstate<=s5;
s5:nstate<=s0;
default:state<=s0;
endcase
end
end
always @(posedge clk or negedge rst_n)//数据输出
begin
if(!rst_n)
data<=0;
else
begin
if(nstate==s0)
data<=0;
else if(nstate==s1)
data<=0;
else if(nstate==s2)
data<=1;
else if(nstate==s3)
data<=0;
else if(nstate==s4)
data<=1;
else if(nstate==s5)
data<=1;
end
end
endmodule
