题解 | #交通灯#

`timescale 1ns/1ns

module triffic_light
    (
		input rst_n, //异位复位信号，低电平有效
        input clk, //时钟信号
        input pass_request,
		output wire[7:0]clock,
        output reg red,
		output reg yellow,
		output reg green
    );
    
    parameter RST=3'd0,GREEN=3'd1,YELLOW=3'd2,RED=3'd3;
    
    reg [1:0] state,next_state;
    reg [7:0] clock_1;
    
    always @(*)
        case(state)
            RST    :next_state = clock_1==8'd8?RED   :   RST;
            GREEN  :next_state = clock_1==8'd1?RED   : GREEN;
            YELLOW :next_state = clock_1==8'd1? GREEN:YELLOW;
            RED    :next_state = clock_1==8'd1?YELLOW:   RED;
            default:next_state = RST;
        endcase
    
    always @(posedge clk or negedge rst_n)
        if(!rst_n)
            state <= RST;
        else
            state <= next_state;
          
    always @(posedge clk or negedge rst_n)
        if(!rst_n)
            clock_1 <= 8'd10;
        else begin
            if(clock_1==8'd1)
                case(state) 
                    GREEN,RST:clock_1 <= 8'd10;
                    YELLOW   :clock_1 <= 8'd60;
                    RED      :clock_1 <= 8'd5 ;
                    default  :clock_1 <= 8'd10;
                endcase
            else if(clock_1==8'd8&&state==RST)
                clock_1 <= 8'd10;
            else if(pass_request&&clock_1>8'd10&&state==GREEN)
                clock_1 <= 8'd10;
            else
                clock_1 <= clock_1 - 1'b1;
        end
    
    always @(posedge clk or negedge rst_n)
        if(!rst_n)begin
            red    <= 1'd0;
            yellow <= 1'd0;
            green  <= 1'd0;
        end else begin
            case(next_state)
                RST    :begin 
                            red    <= 1'd0;
                            yellow <= 1'd0;
                            green  <= 1'd0;
                        end
                GREEN  :begin 
                            red    <= 1'd0;
                            yellow <= 1'd0;
                            green  <= 1'd1;
                        end
                YELLOW :begin 
                            red    <= 1'd0;
                            yellow <= 1'd1;
                            green  <= 1'd0;
                        end
                RED    :begin 
                            red    <= 1'd1;
                            yellow <= 1'd0;
                            green  <= 1'd0;
                        end
                default:begin 
                            red    <= 1'd0;
                            yellow <= 1'd0;
                            green  <= 1'd0;
                        end
            endcase
        end
    
    assign clock = clock_1;
	
endmodule