题解 | #输入序列不连续的序列检测#

使用移位寄存器判别来解决：

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    
    reg [3:0] tmp;
    
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            tmp <= 4'd0;
        else if(data_valid)
            tmp <= {tmp[2:0],data};
        else
            tmp <= tmp;
    
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            match <= 1'd0;
        else if(data_valid && {tmp[2:0],data} == 4'b0110)
            match <= 1'd1;
        else
            match <= 1'd0;

  
endmodule