题解 | #同步FIFO#

改动了一点DPRAM。。。

`timescale 1ns/1ns

/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input clk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  
	,input [WIDTH-1:0] wdata      	
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  
	,output reg [WIDTH-1:0] rdata 		
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge clk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge clk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 

endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output 			reg	wfull	,
	output 			reg	rempty	,
	output wire [WIDTH-1:0]	rdata
);
    reg [$clog2(DEPTH):0] cnt;
    wire wenc, renc;
    reg [$clog2(DEPTH)-1:0] waddr, raddr;
    assign wenc = (winc & !wfull);
    assign renc = (rinc & !rempty);
    
    dual_port_RAM #(.WIDTH(WIDTH), .DEPTH(DEPTH))
    u_DPRAM (
        .clk(clk), .wenc(wenc), .renc(renc), 
        .wdata(wdata), .rdata(rdata),
        .raddr(raddr), .waddr(waddr));
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            wfull <= 1'b0;
        end else if (cnt == DEPTH) begin
            wfull <= 1'b1;
        end else begin
            wfull <= 1'b0;
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            rempty <= 1'b0;
        end else if (cnt == 'b0) begin
            rempty <= 1'b1;
        end else begin
            rempty <= 1'b0;
        end
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            cnt <= 'b0;
        end else if (wenc & !renc) begin
            cnt <= cnt + 1'b1;
        end else if (renc & !wenc) begin
            cnt <= cnt - 1'b1;
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            waddr <= 'b0;
        end else if (wenc) begin
            waddr <= waddr +1'b1;
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            raddr <= 'b0;
        end else if (renc) begin
            raddr <= raddr +1'b1;
        end
    end
endmodule