米利状态机，三段式搞定。

第一个always时序初态和次态，第二个always组合逻辑描述状态转移，第三个always组合逻辑描述输出。输出可以不合并，编译器会帮你优化的。

`timescale 1ns/1ns

module seq_circuit(
   input    wire       C,
   input    wire       clk,
   input    wire       rst_n,
 
   output   reg        Y   
);
    
    localparam s1 = 4'b0001;
    localparam s2 = 4'b0010;
    localparam s3 = 4'b0100;
    localparam s4 = 4'b1000;
    reg[3:0] state;
    reg[3:0] next_state;
    
    always @(posedge clk or negedge rst_n)begin
        if(!rst_n)
            state <= s1;
        else
            state <= next_state;
    end

    always @(*)begin
        if(!rst_n)
            next_state <= s1;
        else begin
            case(state)
                s1:begin
                    if(C == 1'b0)
                        next_state = s1;
                    else
                        next_state = s2;        
                end
                s2:begin
                    if(C == 1'b0)
                        next_state = s4;
                    else
                        next_state = s2;       
                end
                s3:begin
                    if(C== 1'b1)
                        next_state = s3;
                    else
                        next_state = s1;        
                end                
                s4:begin
                    if(C == 1'b0)
                        next_state = s4;
                    else
                        next_state = s3;        
                end
                default:next_state = s1;
            endcase
        end
    end
    
    always @(*)begin
        if(!rst_n)
            Y = 1'b0;
        else begin
            case(state)
                s1:begin
                        Y = 1'b0;
                end
                s2:begin
                        Y = 1'b0;
                end
                s3:begin
                    if(C== 1'b0)
                        Y = 1'b0;
                    else
                        Y = 1'b1;
                end                
                s4:begin
                        Y = 1'b1;
                end
                default:Y = 1'b0;
            endcase
        end
    end
    
    
endmodule