题解 | #RAM的简单实现#

主要是初始化用for写，开始我在always块中用了generate，发现报错了，后来一想generte是个生成块，应该放在always，assign以及instance外面，always内部循环用integer + for实现

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);
    //prameter 
    parameter WIDTH = 4;
    parameter DEPTH = 8;
    
    //defination
    reg [WIDTH - 1 : 0] RAM [0 : DEPTH - 1];

    //output 
    integer i;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) begin
               for(i = 0; i < DEPTH; i = i + 1) begin
                   RAM[i] <= 'd0;
               end
        end
        else if(write_en) RAM[write_addr] <= write_data;
    end
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) read_data <= 'd0;
        else if(read_en) read_data <= RAM[read_addr];
        else read_data <= 'd0;
    end
endmodule