使用动态生成语句：generate—for，实现重复例化；

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);
    wire [3:0] g, p;
    wire [3:0] c_temp, pc_temp;
    genvar i;
    generate
        for(i=0;i<4;i=i+1)
            begin:some
                xor p_gate (p[i], A_in[i], B_in[i]);
                and g_gate (g[i], A_in[i], B_in[i]);
                
                if(i == 0) begin
                    and pc_gate (pc_temp[i], p[i], C_1);
                    xor s_gate (S[i], p[i], C_1);
                end
                else begin
                    and pc_gate (pc_temp[i], p[i], c_temp[i-1]);
                    xor s_gate (S[i], p[i], c_temp[i-1]);
                end
                
                or c_gate (c_temp[i], g[i], pc_temp[i]);
                
            end
    endgenerate
    
    assign CO = c_temp[3];
    
endmodule