As a member of backend team, you will be responsible for the physical implementation (RTL2GDS) of a highly complex SOC utilizing state of the art process technology.
Responsibility include but not limited to:
- Work with FE team to understand chip architecture and drive physical aspects early in design cycle.
- Joining in the improvement of full back-end flow from RTL to GDSII, including synthesis, place&route, STA, irdrop, DRC/LVS.
- Top level floorplan, block implementation, timing and physical sign-off, power integrity.
岗位要求
Major in CS & EE
- Strong communication skills.
- Basic skills in linux/cshell/bash/make.
- familiar with one of below languages: tcl/perl/python, python is a plus.
- Experience in physical design or mainstream EDA tools is a plus
1、计算机、电子工程、数学、通信、自动化等相关专业,本科及以上学历;
2、对并行计算、异构计算和计算性能优化有浓厚兴趣;
3、熟悉C/C++编程语言。
满足以下一种或多种条件者优先:
A. 了解各种机器学习/图像处理算法;
B. 了解OpenMP、CUDA并行编程模型;
C. 了解编译原理,了解GCC、LLVM等开源编译器相关实现;
D. 高性能库(如OpenBLAS、MKL、cuDNN等)开发和性能调优经验。
本岗位需要笔试
岗位要求:
1、专业不限,本科及以上学历;
2、熟悉机器学习/深度学习/图像处理相关算法;
3、熟悉C/C++编程语言;
满足以下一种或多种条件者优先:
A. 熟悉OpenCV/Matlab使用;
B. 了解计算机体系结构;
C. 了解Tensflow/Mxnet/Caffe等深度学习平台架构;
D. Linux编程开发经验。