VHDL以下哪项是结构体architecture声明和定义的

ARCHITECTURE architecture_type OF entity_name IS
Declarations_for_architecture;
BEGIN
Code;
….
END architecture_name;

ARCHITECTURE architecture_name OF entity_name IS
BEGIN
Declarations_for_architecture;
Code;
….
END architecture_name;

ARCHITECTURE architecture_type OF entity_name IS
BEGIN
Declarations_for_architecture;
Code;
….
END architecture_type;

ARCHITECTURE architecture_name OF entity_name IS
Declarations_for_architecture
BEGIN
Code;
….
END architecture_name;