设计一个**异步低电平复位**的D触发器，以下Verilog

always @(posedge clk) begin if (!rst_n) q <= 0; else q <= d; end // 同步复位

always @(posedge clk or negedge rst_n) begin if (!rst_n) q <= 0; else q <= d; end // 异步复位

always @(posedge clk or posedge rst_n) begin if (rst_n) q <= 0; else q <= d; end // 异步高复位

always @(posedge clk) begin if (rst_n) q <= d; else q <= 0; end // 同步高复位