首页 > 试题广场 >

If the data path takes up to t

[问答题]

If the data path takes up to three clock cycles, see the circuit below, please specify the multicycle constrains using SDC command. Note that hold check need to stay as it was in a single cycle setup case.

aoyasun

set_multicycle_path 3 -setup -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

set_multicycle_path 2-1 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

发表于 2019-07-01 17:46:16 回复(3)

Tjoker

set_multicycle_path 3 -setup -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

set_multicycle_path 2 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

发表于 2019-09-02 09:48:42 回复(0)

zhangxiaohe666

#定义名为CLKM、周期宽度为10nm的时钟

set_clock -name CLKM -period 10 [get_potrs CLKM]

#将UFF1/CK的时钟捕获沿向后推迟到距离UFF0/CK三个时钟周期

set_multicycle_path 3 -setup -from [get_pins UFF/Q] to [get_pins UFF1/D]

#hold check edge变为到了第三个周期起始位置，即T20ns ，将其拉回到T0ns

set_multicycle_path 2 -hold -from [get_pins UFF/Q] to [get_pins UFF1/D]

发表于 2020-08-19 10:08:23 回复(0)

不是所有萌新都叫特能输

set_multicycle_path 3 -setup -from [get_pins UFF0/Q] -to [get_pins UFF1/D]
set_min_delay 0 -from -from [get_pins UFF0/Q] -to [get_pins UFF1/D]
#set_multicycle_path 2 -hold -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

set_min_delay的方式是<<高级ASIC芯片综合>>推荐的约束方式, 参考13.2.1小节

发表于 2023-06-30 17:43:09 回复(0)