Please write verilog code to represent a single bit DFF of synchronized reset and asynchronized reset.
module DFF1( output reg q, input d, input clk,rst ); always @(posedge clk) //synchronization begin if(!rst) q<=0; else q<=d; end endmodule module DFF2( output reg q, input d, input clk,rst ); always @(posedge clk or negedge rst) //asynchronization begin if(!rst) q<=0; else q<=d; end endmodule
module dff_syn( input clk, input reset, input d, output q ); always@(posedge clk)begin if(reset) q <= 0; else q <= d; end endmodule
module dff_asyn( input clk, input areset, input d, output q ); always@(posedge clk&nbs***bsp;posedge arest)begin if(areset) q <= 0; else q <= d; end endmodule
`include "type_mux.v" module #( parameter TYPE = 0 )( input i_data , input rst_n , output o_data ); reg data; `ifdef ASYNC_RST always@(posedge clk) if(!rst_n) data <= 'd0; else data <= i_data; `endif `ifdef SNYC_RST always@(posedge clk&nbs***bsp;negedge rst_n) if(!rst_n) data <= 'd0; else data <= i_data; `endif assign o_data = data;