1.电子/通信/微电子/自动化 等相关专业， 本科以上学历 2.熟练掌握UVM, SystemVerilog 3.具备模块级或者子系统级等验证经验 4.具有编写自动化脚本或借助AI 提升效率的经验者佳. 5.对技术充满热情,具有很强责任心,良好的沟通表达能力和团队合作精神.

1. 计算机、通信、自动化等相关专业， 2. 硕士学历 3. 3年以上嵌入式系统开发经验 4. 精通C/C++/python 5. 具备以下条件者优先考虑： -ARM底层开发经验 -QNX或者其他虚拟机开发经验 -HarmonyOS、aliOS开发经验 -联发科或高通平台系统开发经验 -linux kernel或bootloader开发经验 -性能优化经验、linux kernel调度优化经验

1. 计算机、通信、自动化等相关专业， 2. 本科及以上学历 3. 2年以上嵌入式系统开发经验 4. 精通C/C++/python 5. 具备以下条件者优先考虑： -linux / Android performance调优经验。 -Android framework 开发/维护经验。

1. 微电子/电子信息/计算机科学与技术专业，硕士及以上学历 2. 具有项目责任感和团队合作精神；沟通能力强，执行能力强；认真负责，考虑问题细致谨慎，能够独立分析解决问题 3. 熟悉System Verilog/VMM/UVM方法学/C/SVA 加分项： a) 熟悉AMBA协议和ARM based SoC架构； b) 具备DRAM（especially HBM，LPDDR系列） 相关领域经验 ； c) 熟悉脚本语言，比如Python、Perl或者Tcl等； d) 有soc 产品成功tapeout经验； e) 熟悉Formal verification

1. Master's degree in Computer Science/Electronics or related fields (from a 211 or higher institution), with at least 5 years of experience in embedded Linux or Android software development, and over 2 years of experience in PMIC driver development and support on Qualcomm/MTK platforms, or relevant experience with major PMIC manufacturers such as TI, Infineon, MPS, NXP, etc. 2. Familiar with PCB hardware schematics and common electronic components, proficient in the working principles of Buck/LDO/Boost devices, and knowledgeable about common PMIC hardware interfaces such as I2C/SPMI/PMbus communication protocols. 3. Proficient in C/C++ programming, familiar with Linux/Windows kernel PEP driver development, and experienced with software development tools (e.g., git, JIRA, CQ, etc.). 4. Familiar with Linux/Windows system power management architecture and power supply solutions, understanding of power-saving technologies such as Clock/DVFS/Suspend/Thermal, and knowledge of ARM PSCI/SCMI software interfaces. 5. Experience with notebook PC manufacturers or brand car manufacturers in intelligent cockpit projects is preferred, with additional preference for those familiar with PMIC software and hardware virtualization and function safety. 6. Strong logical thinking, communication skills, and teamwork spirit, with a priority for project-oriented mindset. 7. CET-4 level English or above, capable of reading English technical specifications, writing English technical documents, and supporting overseas customers.

1）学历 /专业 本科以上，计算机及相关专业 2）工作经验：有两年以上嵌入式开发经历，具有Display driver相关工作经验优先； 3）专业技能：熟练掌握C语言编程、嵌入式软件研发，有驱动开发经验者优先； 4）英语要求：能够阅读英文技术规格，能撰写档； 5）其他：做事有耐心，良好的沟通能力 、语言表达能力

1. 计算机硬件或软件相关学科硕士（211以上學校）毕业，至少4年嵌入式Linux或Android软件开发经验， 2年以上Power相关工作经验（低功耗，power feature, PMIC, thermal等） 2. 了解神经网络编程框架SDK设计、开发、性能测试和优化,有了解GAI大模型者优先。 3. 有实际Linux/Android系统电源管理架构项目经验，对power 功耗有优化经验优先。 4. 精通C/C++编程，对Linux Driver开发熟悉，熟悉软件开发工具和脚本语言(如git,CMake, shell等)。 5. 较强逻辑思维能力、沟通能力及团队合作，項目優先精神。 6. 四级以上，能够阅读英文技术规范，能够撰写英文技术文档

1. Major in computer/electronic information/electronic communications, proficient in C language development, with more than 3 years of software development experience 2. Proficient in Linux driver design, development, and debugging. 3. Have a basic understanding of hardware circuits and be proficient in using an oscilloscope 4. Good English listening, speaking, reading, and writing skills

Skills/Experience • Strong critical thinking and creative problem-solving skills. • Proficient on Verilog and SystemVerilog, able to develop synthesizable and behavioral code • Deep knowledge on digital design fundamentals, including Finite State Machine, etc. • Good Understanding of simple Analog Mixed-Signal design elements such as op-amps, etc. • Able to read schematics of Analog or Custom Design is a plus • Able to run and debug SPICE simulations is a plus • Hands on experiences with EDA tools such as Cadence Virtuoso DE is a plus • Previous experience on analog behavioral modeling is a huge advantage. • Ability to develop SystemVerilog Assertion is a strong plus • Experience on Digital and/or AMS Functional Verification is a strong plus • Knowledge of systems such as SERDES, PLL and/or WiFi, etc., is a strong plus • Ability to develop Verilog-A or Verilog-AMS models is a strong plus • Ability to develop Model Validation Environment is a strong plus • Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus. Education Requirements • BS degree and a minimum of 3 years of relevant industry experience, or • MS degree with a minimum of 2 years of relevant industry experience • Senior positions to be offered to candidates with proven expertise in the relevant field

Skills/Experience • Strong critical thinking and creative problem-solving skills. • Proficient on Verilog and SystemVerilog, able to develop synthesizable and behavioral code • Deep knowledge on digital design fundamentals, including Finite State Machine, etc. • Good Understanding of simple Analog Mixed-Signal design elements such as op-amps, etc. • Able to read schematics of Analog or Custom Design is a plus • Able to run and debug SPICE simulations is a plus • Hands on experiences with EDA tools such as Cadence Virtuoso DE is a plus • Previous experience on analog behavioral modeling is a huge advantage. • Ability to develop SystemVerilog Assertion is a strong plus • Experience on Digital and/or AMS Functional Verification is a strong plus • Knowledge of systems such as SERDES, PLL and/or WiFi, etc., is a strong plus • Ability to develop Verilog-A or Verilog-AMS models is a strong plus • Ability to develop Model Validation Environment is a strong plus • Scripting and automation skills: Unix/Linux shell programming, Perl, Python, Makefile, and revision management (e.g., CVS, Perforce, etc.) is a plus. Education Requirements • BS degree and a minimum of 3 years of relevant industry experience, or • MS degree with a minimum of 2 years of relevant industry experience • Senior positions to be offered to candidates with proven expertise in the relevant field

1、硕士及以上学历，1年以上经验，计算机、微电子、电子工程、通信工程、自动化等相关专业。 2、 学习意愿高，快速学习能力和解决问题能力。 3 、有创造力，善于系统性思考解决问题。 4 、开放，友善，有效的沟通方式和技巧。 5 、有RLT design/integration/post-silicon 等一项或多项相关经验 如有以下任何相关经验都是加分项: 1）有IC Sensor开发或研究经验优先录用; 2）熟悉integration 或者DFT flow，并有自动化流程开发经验的。 3）懂IC设计，又熟悉data mining 或者大数据相关技术。 3）对IC 全流程有较深理解。

1. 计算机/电子信息工程或相关领域，本科/硕士及以上学历,三年或以上ASIC领域工作经验 2. 熟悉Verilog，熟悉ASIC前端设计的流程 3. 熟悉Synopsys DC/DFTC/TetraMAX/VCS 或Mentor Tessent平台的使用 4. 熟悉脚本语言开发：Makefile/Tcl/Perl/Python等 5. 具备良好的英文交流技巧和Presentation经验 6. 具备认真细致的工作态度，对测试技术充满好奇心，勇于承担责任，乐于帮助同事 加分项： 1）具备ASIC设计经验，如：RTL coding, Synthesis, P&R, STA timing signoff, IR Analysis等经验者优先； 2）熟悉IEEE1149.1/1149.6/1500标准, 有boundary scan经验者优先；具备可测性理论知识和概念优先 3）熟悉Spyglass DFT工具分析RTL testability/DRC check 者优先； 4）熟悉Synopsys DFTMAX/Mentor EDT测试压缩架构, 精通STIL语言者优先； 5）熟悉主流的ATE（UltraFlex/V9300）测试开发flow, pattern conversion, Timing-set, pattern debug, Shmoo等工作者优先。

1.计算机、电子、通信 、自动化等相关专业，本科3年以上经验，硕士2年以上工作经验 2.熟悉计算机网络，TCP/IP 协议； 3.熟悉Linux 系统， 熟练掌握 C语言 4.熟悉嵌入式系统知识,、了解嵌入式系统常用硬件模块原理，掌握嵌入式系统调试技能, 有底层开发经验更佳 5.有强烈上进心，乐于学习新知识适应新环境，乐观自信，挑战自我不断追求卓越 6.能承担较大工作压力，具备良好的沟通能力和团队合作精神

1.本科及以上学历，电子工程/通讯/计算机等相关工科专业 2.具备5年以上的电子行业的产品管理经验 3.有工程技术经验，尤其是手机、汽车电子、笔记本行业经验者优先考虑 4.责任心与抗压能力强、沟通表达力强 5.具备一定的市场分析及判断能力，有良好的客户导向意识 6.有一定的英语基础

1. 本科及以上学历，电子，计算机科学相关专业学历 2. 汽车电子行业至少6年工作经验，智能座舱，ADAS相关PM经验优先考虑 3. 逻辑思维清晰，可清晰分析市场动态与客户属性，根据竞争对手状态产出相应策略 4. 需要较强的沟通能力 5. 工作认真负责，自我驱动力强

1.本科及以上学历，10年以上行政管理工作经验 2.有在至少500人以上规模企业的工作经验，有丰富的供应商管理经验，能够有效协调和管理供应商 3.具备较好的逻辑思维能力、数据分析能力和问题解决能力，能够快速应对和解决突发事件 4.具备良好的沟通协调能力、团队合作能力；能熟练使用各类办公软件/工具提升工作效能 5.具备较强的责任心、执行力及创新思维 6.适应快节奏工作环境，能够在压力下保持高效

1，本科及以上学历，电子、通讯、自动化、汽车类等相关专业，5年以上硬件设计经验，有手机设计经验更佳。 2，优秀的沟通和协调能力，善于学习总结，自我驱动力强，具备长期快速学习新知识新技术的能力 3，熟悉手机行业国家标准和国际标准，较强的硬件设计和项目调试经验，熟悉整个硬件产品到上市的周期，有实际项目量产经验。 4，有手机/平板/智能穿戴设备等电子产品设计工作经验优先，具备独立承担大型项目硬件SE经验，熟悉芯片设计应用和技术细节更佳 5，英文良好，口语佳更好