我们正在寻找一名 LLM/ML 开发人员，他将成为构建可扩展且具有弹性的数据分析/ML 平台的关键贡献者。

1. Develop AI model related to Electro-thermal / Electro-magnetic / Structural simulation. 2. Implement algorithm for mesh processing, encoding-decoding. 3. Track newest technological development and research directions in artificial intelligence; leading the research on generalization ability and interpretability of large models in complex scenarios. 4. Apply AI algorithms into Cadence products to improve the accuracy and performance.

编译器相关软件开发。

- Develop and maintain embedded firmware for USB, UCIe, PCIe, and DisplayPort PHY IPs - Perform pre-silicon and post-silicon firmware verification and validation - Develop test scripts, automation tools, and GUI using Python - Collaborate with hardware design teams to optimize firmware-hardware interactions

我们正在寻找一名 LLM/ML 开发人员，他将成为构建可扩展且具有弹性的数据分析/ML 平台的关键贡献者。

1. 三维几何引擎内核研发。 2. 数字几何处理算法研发。

1. 三维几何引擎内核研发。 2. 数字几何处理算法研发。

设计领域：晶体管，电阻，电容的匹配，电源和地的耦合，差分对的信号通路等。 熟练使用Cadence布局工具Virtuoso XL和Assura（有ICADVM版本经验者优先）。 能够与其他模拟IC 电路布局协调，确保可靠、高效、一致和成功地交付模拟IC电路布局。 对IC设计技术和流程/方法有基本的了解（有台积电或三星FINFET经验者优先）。 熟悉模拟IC芯片组装，包括布局规划和模块布局。 具有进行DRC/LVS分析和推荐适当解决方案的实际经验（有EMIR修复经验者优先）。

设计领域：晶体管，电阻，电容的匹配，电源和地的耦合，差分对的信号通路等。 熟练使用Cadence布局工具Virtuoso XL和Assura（有ICADVM版本经验者优先）。 能够与其他模拟IC 电路布局协调，确保可靠、高效、一致和成功地交付模拟IC电路布局。 对IC设计技术和流程/方法有基本的了解（有台积电或三星FINFET经验者优先）。 熟悉模拟IC芯片组装，包括布局规划和模块布局。 具有进行DRC/LVS分析和推荐适当解决方案的实际经验（有EMIR修复经验者优先）。

验证数字后端设计工具Innovus，确保产品在整个后端设计流程中可以高效工作。 研判客户问题，推动技术进展，与研发及产品部门协作持续提高Innovus质量性能。

Deliver/implement SoC and ASIC chip. The engineer should be able to act as a good team member Specific duties include: Proficiency in SoC and ASIC spec definition, micro-architecture bring-up, RTL coding, synthesis, STA and testing Proficiency in SoC and ASIC design flow and sign-off, especially front-end Frontend design experience for successful SoC/ASIC chip tape-out

Deliver/implement SoC and ASIC chip. The engineer should be able to act as a good team member Specific duties include: Proficiency in SoC and ASIC spec definition, micro-architecture bring-up, RTL coding, synthesis, STA and testing Proficiency in SoC and ASIC design flow and sign-off, especially front-end Frontend design experience for successful SoC/ASIC chip tape-out

- 高速IP数字物理设计及实现 - 负责数字物理设计及实现，从netlist到GDS，包括Floorplan，P&R，Physical verification，DFM - 团队合作，和前端和模拟团队合作

- 高速IP数字物理设计及实现 - 负责数字物理设计及实现，从netlist到GDS，包括Floorplan，P&R，Physical verification，DFM - 团队合作，和前端和模拟团队合作

- 设计，模拟和验证10Gbps 以上的高速SerDes接口电路。 - 建立高速模拟电路模块的AMS模型和支持在数字集成中的IP联合验证。

- 设计，模拟和验证10Gbps 以上的高速SerDes接口电路。 - 建立高速模拟电路模块的AMS模型和支持在数字集成中的IP联合验证。

- BS in Computer Science or related area with 4+ years of working experience or equivalent in EDA/CAD tool development - 4+ years of C++/Qt/MFC experiences - Strong professional experience developing scalable applications - Both Linux and Windows development experiences are preferred - Architect, design and develop high quality, secure, performant services - Work closely with product owners and team to understand and elaborate

- 高速IP数字物理设计及实现 - 负责数字物理设计及实现，从netlist到GDS，包括Floorplan，P&R，Physical verification，DFM - 团队合作，和前端和模拟团队合作

-Responsible for the IP subsystem and SoC verification based on metric driven methodology -Developing and using verification components(UVC, VIP, AVIP) -Developing constrained random verification environment, responsible for coverage closure

To provide key technical support in digital IC design implementation, product demonstration, and sales presentations. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis. Synthesis experience will be a plus. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs. To play a leading role among other team members, while receive little instruction on routine and general assignments.