2025 Summer Intern-Standard Cell Library Design Engineer
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Job Responsibilities
1. Standard Cell Library Development & Optimization
o Participate in the schematic design, physical layout design, and simulation verification of standard cell libraries.
o Optimize the library's performance-power-area (PPA) metrics to meet design requirements across various process nodes.
o Generate various library database views for standard cells, including GDS/CDL/LEF/NDM/LIB/DB/Verilog/ATPG/APLCHAR/PGV, etc.
o Library database views QA work to ensure database quality.
o Support standard library user guide documentation and maintenance.
2. EDA Tool Usage & Script Development
o Proficiently use EDA tools (e.g., Cadence Virtuoso, Spectre, Innovus; Synopsys Primetime, ICC, Calibre) for library design, simulation, and verification.
o Develop TCL/Perl/Python/Skill scripts to automate design flows and improve efficiency.
Requirements
1. Education Background
o Master's degree or above in Microelectronics, Integrated Circuit Design, Electronic Engineering, Computer Science, or related fields.
2. Technical Skills
o Strong foundation in digital circuit design, familiarity with CMOS technology and semiconductor physics.
o Understanding of standard cell library design flows and basic concepts in timing analysis and power optimization.
o Familiarity with Linux operating systems; TCL/Perl/Python/Skill scripting skills are preferred.
3. Tools & Software Experience
o Prior experience with EDA tools (e.g., Cadence, Synopsys) for digital circuit design is a plus.
o Experience with layout design tools (e.g., Virtuoso), circuit simulation (Spectre/HSPICE), or static timing analysis (e.g., PrimeTime) is a plus.
