【26届可投】ASIC Engineer Intern, Design/Verification/Power Analysis

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today.

We have multiple directions for ASIC Engineer development, shared them in a single JD, including:

Direction 1: IP Design/Verification

Direction 2: SOC Design/Verification/Formal Verification

Direction3：SOC Infrastructure/Methodology

Direction :4: Architectural Energy Modeling

What you’ll be doing:

·      Micro architecture design.

·      RTL (Verilog) coding.

·      Design implementation using Synopsys/Cadence tools.

·      Simulate, debug and write tests to verify design functionality and performance (IP/SOC design/verification direction).

·      Apply cutting edge Formal Technologies to fully verify design functionality (Formal Verification direction).

·      Works on both generic and custom products (Custom SOC).

·      Methodology in any of above areas (Architectural Energy Modeling).

What we need to see:

·      MS degree from EE/CS or related majors from a prestigious university.

·      Good knowledge in digital circuit design.

·      Experience in using Verilog HDL.

·      Experience in various of ASIC EDA tools.

·      Fluent in English reading and writing.

·      Self-motivated, good team player.

Ways to stand out from the crowd:

·      Proven ability to work independently as well as in a multi-disciplinary group environment

·      Good command of C/C++ programming language.

·      Mastery in one of the below areas

# Video codec.

# Encryption/Decryption.

# Processor architecture.

# Signal/image processing.

# Pattern recognition/machine learning.

# Data science.

# System on Chip.

# Memory interface.

·      Understand ASIC design flow, hands-on experience in using industrial standard EDA tools is a plus.

·      Basic DFT knowledge including Boundary Scan, 1500, MBIST, Scan, ATPG is a plus

·      Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is a plus

·      Proficient user of script language like Perl, Python or TCL is plus

·      Experienced in FPGA/EMU related implementation is a plus

·      Experienced in Linux PCIE driver or other SW works is a plus

·      Experienced in SystemC or UVM or SV or SCE-MI or other standards is a plus

·      Knowledge in Formal Techniques is a plus

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.