暂时没有符合条件的职位

研发 上海
详情 收起

薪酬:20K-40K  |  学历要求:本科及以上  |  工作年限:3-5年

岗位职责
Responsible for designing, developing, and debugging EDA software. This role will focus on data hierarchy, concurrent algorithms, and distributed processing areas to maintain and improve compression, performance, and scalability.
岗位要求
Requirements: · M.S. or Ph.D. in Computer Science, Engineering, or Physical Sciences . · Familiar with software development and testing methodologies · Proficient in C/C++, experience in developing complex programs is a plus. · Good problem solving skills and the ability to communicate in English.
其他 厦门
详情 收起

薪酬:180K-300K  |  学历要求:硕士及以上  |  工作年限:3-5年

岗位职责
Job Title:C/C++软件开发工程师 Location:Xiamen Were looking for Senior R&D Engineer to join our team. Does this sound like a good role for you? In this role you will be responsible for designing, developing, troubleshooting, or debugging software programs. Develops software tools including operating systems, compilers, routers, networks, utilities, databases and internet-related tools. Determines hardware compatibility and/or influences hardware design. Exercises independent judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project. Determines and develops recommendations to solutions. Works on team-driven or task-oriented projects. May guide more junior peers with aspects of their job. Networks with senior internal and external personnel in own area of expertise.
岗位要求
Key Qualifications · Experience in programming software for operating systems, utilizing machine assembly and/or job control languages, and some knowledge of software capabilities · Experience on development of complex software projects · Familiarity with C/C++ coding · Strong background in data structures and algorithms · Strong desires to learn and explore new technologies · Good analysis and problem-solving skills · Prior knowledge and experience of EDA tool development are preferred · Typically requires a minimum of 3 years of related experience · Solid understanding of specialization area plus working knowledge of one other related area
其他 南京
详情 收起

薪酬:15K-20K  |  学历要求:本科及以上  |  工作年限:3-5年

岗位职责
Job Title: Digital Design Platform Validation Engineer Descriptions: Platform Validation Engineer is responsible for validating the industry leading SoC implementation products and flow solutions, including “Design Compiler NXT”, “IC Compiler II”, “Formality” and next generation RTL to GDS Digital Design Platform “Fusion Compiler”. Under this role, a Platform Validation engineer will - Study and understand customer requirements and R&D functional specifications, design and execute testing plan to validate new features (new functions, Performance/Power/Area improvements, Advanced node 5nm/3nm enablement etc.) - Using real top-tier customer designs and/or creating new designs to ensure the quality of new features. - Debug and identify the root causes of functionality issues, flow issues including complicated PPA (Performance/Power/Area) issues in RTL2GDS design flow. - Analyze customer issues and customer usage/flow, propose coverage improvement plan and enhancement requests to improve the products. - Design and develop validation solutions/products in Python, C/C++, Perl, Tcl, etc. to improve the testing efficiency and solve complicated EDA software testing challenges such as Machine Learning based testing automation, PPA big data handling etc.
岗位要求
Requirements: - BS/MS in EE, Microelectronics, CS or relevant (也欢迎2021应届毕业生) - Self-motivated, good team worker and great learner - Good verbal and written communication skills in both Chinese and English - Passionate in learning and supporting new evolving technologies – 5nm/3nm, low power design, 3D IC, machine learning, cloud, data mining etc. - Experience in SoC design or CAD – Verification, Synthesis, Test, Place & Route, STA, Physical Verification, is a strong plus - Experience in software testing & software testing automation is a strong plus - Knowledge and experience in one or more of the following CS fields is a strong plus: · Programming language (C/C++, Shell, TCL, Perl, Python etc.) · Unix/Linux operating system
研发 北京
详情 收起

薪酬:150K-300K  |  学历要求:本科及以上  |  工作年限:0-1年

岗位职责
Synopsys offers a broad portfolio of high-quality, silicon-proven IP solutions for the most widely used interfaces such as PCI Express, USB, DDR, SATA, HDMI, MIPI, and Ethernet. This position will be responsible for technical support of customers using Synopsys DesignWare Cores IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. Responsibilities Include - Discussing with customer on their application and SoC design, Capturing and understanding their design requirements, Proposing DW IP solutions to best-fit customer requirements with competitive PPA - Providing direct technical support and assistance to enable customers to use DW IP successfully - Working with the sales teams to manage the IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships - Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across the business units and with other product line teams to provide high quality support for customers. - Writing application notes, attend technical conferences and review projects and protocol specifications. - Providing technical guidance and support to the sales team during calls, meetings, and marketing events.
岗位要求
Location:北京市海淀区科学院南路2号 融科资讯中心 Requirements: - Bachelors and/or Master’s Degree in Electrical and/or Electronic Engineering, Computer Engineering or Computer Science. - Experience with one or more I/O protocols, such as Ethernet, USB, DDR, HBM2, PCIe, CCIX, MIPI, SATA, HDMI, Mobile Storage and Multi-protocol Serdes are preferred. - An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred. - Minimum of 5 years relevant experience in ASIC/SoC front-end design including RTL coding in Verilog, logic and clock tree synthesis, static timing analysis, equivalence checking. - Full understanding of digital design methodologies and tools including formal verification. - Ideally have experienced at least one ASIC/SoC tape-out from concept to full production. - Silicon debug and troubleshooting skills are highly desirable. - Technically creative, results oriented with the ability to manage multiple tasks efficiently including customer support issues and priorities. - Strong communication skills and ability to interact with customers as well as peers. - High degree of self-motivation and personal responsibility. - Strong analytical, reasoning and problem solving skills and attention to details
研发 上海
详情 收起

薪酬:350K-450K  |  学历要求:本科及以上  |  工作年限:3-5年

岗位职责
Job Title: Interface IP Application Engineer( Pre-sales) Location: Shanghai/ Shenzhen Job Description and Requirements A presales AE (Application Engineer) is responsible for providing technical support for Synopsys DesignWare Intellectual Property (DW IP) in presales stage within China with primary focus on Northern China region. A presales AE’s responsibilities include: 1) Discussing with customer on their application and SoC design, Capturing and understanding their design requirements for Interface IP, Preparing IP technical solution with BU R&D to meet the requirements, Co-working with customer to update chip microarchitecture based on IP characteristics 2) Studying high speed interface protocol update, joining IP product update training and technical conference, and deepening expertise on Interface IP by systematic learning and hands-on IP practice as configuration, synthesis and verification 3) Working with sales teams to manage IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships 4) Providing direct technical support and assistance if needed to enable customers to use DW IP successfully 5) Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across business units and with other product line teams to provide high quality support for customers. 6) Providing technical guidance and support to sales team during calls, meetings, and marketing events.
岗位要求
Requirements: Qualified applicants should have a BSEE, MSEE preferred, at least 5+ years relevant experience in ASIC/FPGA designs. Exposure to IP-based SOC design and real tape-out experience are highly desired. Design, integration or verification experience with one or more high speed interface, such as Ethernet, USB, DP, DDR, HBM2e/2, PCIe, CCIX, MIPI, HDMI, Mobile Storage and Multi-protocol Serdes is required. An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred. Customer interaction related experience is preferred. Technical or domain knowledge on 5G IoT, 5G mobile, AI and Automotive is a plus. The ability to conduct technical meetings, presentations, product demonstrations, and training to customers and the sales team is required. Good written and verbal communication skills in both Mandarin and English are required.
研发 深圳
详情 收起

薪酬:350K-450K  |  学历要求:本科及以上  |  工作年限:3-5年

岗位职责
Job Title: Interface IP Application Engineer( Pre-sales) Location: Shenzhen Job Description and Requirements A presales AE (Application Engineer) is responsible for providing technical support for Synopsys DesignWare Intellectual Property (DW IP) in presales stage within China with primary focus on Northern China region. A presales AE’s responsibilities include: 1) Discussing with customer on their application and SoC design, Capturing and understanding their design requirements for Interface IP, Preparing IP technical solution with BU R&D to meet the requirements, Co-working with customer to update chip microarchitecture based on IP characteristics 2) Studying high speed interface protocol update, joining IP product update training and technical conference, and deepening expertise on Interface IP by systematic learning and hands-on IP practice as configuration, synthesis and verification 3) Working with sales teams to manage IP activities in the region to achieve a high customer satisfaction and for building strong customer relationships 4) Providing direct technical support and assistance if needed to enable customers to use DW IP successfully 5) Managing DW IP technical support requirements and needs for existing or prospective customers. This role requires AE to work and coordinate across business units and with other product line teams to provide high quality support for customers. 6) Providing technical guidance and support to sales team during calls, meetings, and marketing events.
岗位要求
Requirements: Qualified applicants should have a BSEE, MSEE preferred, at least 5+ years relevant experience in ASIC/FPGA designs. Exposure to IP-based SOC design and real tape-out experience are highly desired. Design, integration or verification experience with one or more high speed interface, such as Ethernet, USB, DP, DDR, HBM2e/2, PCIe, CCIX, MIPI, HDMI, Mobile Storage and Multi-protocol Serdes is required. An understanding of system design and logic design using an HDL language, synthesis, simulation and verification CAD tools is essential. Hands on experience with DC or equivalent is preferred. Customer interaction related experience is preferred. Technical or domain knowledge on 5G IoT, 5G mobile, AI and Automotive is a plus. The ability to conduct technical meetings, presentations, product demonstrations, and training to customers and the sales team is required. Good written and verbal communication skills in both Mandarin and English are required.

发布者

Synopsys
企业用户:Synopsys
  • 平均简历处理率 8%
  • 平均简历处理时间 76天

Synopsys

查看其他3个职位>>

芯片,半导体

杨浦区

北京 上海 深圳 南京 厦门 武汉 西安 其他

  • 笔试

    0
  • 面试短评

    0
  • 面经

    3