题解 | 含有无关项的序列检测

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);

	reg [8:0] areg;
// 位移寄存器方法只能用于可重叠序列检测
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			areg <= 'd0;
		end
		else begin
			areg <= {areg[7:0],a};
		end
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			match <= 1'b0;
		end
		else begin
			casex(areg)
				9'b011xxx110: match <= 1;
				default: match <= 0;
			endcase
		end
	end
  
endmodule