题解 | 脉冲同步电路

`timescale 1ns/1ns

module pulse_detect(
	input 				clk_fast	, 
	input 				clk_slow	,   
	input 				rst_n		,
	input				data_in		,

	output      		dataout
);

// 缺点： 若是两个脉冲隔的太近了，则检测不到

reg Q;
always@(posedge clk_fast or negedge rst_n)begin
	if(!rst_n)begin
		Q<=1'b0;
	end
	else if(data_in) begin
		Q<=~Q;
	end
	else begin
		Q<=Q;
	end
end

reg data_1;
reg data_2;
reg data_3;
always@(posedge clk_slow or negedge rst_n)begin
	if(!rst_n)begin
		data_1 <= 1'b0;
		data_2 <= 1'b0;
		data_3<=1'b0;
	end else begin
		data_1 <= Q;
		data_2 <= data_1;
		data_3<=data_2;
	end
end


assign dataout = data_2 ^ data_3;

endmodule