题解 | 状态机与时钟分频

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

parameter S1 = 3'b000;
parameter S2 = 3'b001;
parameter S3 = 3'b010;
parameter S4 = 3'b100;

reg [2:0] state;
reg [2:0] nextstate;

always@(posedge clk or negedge rst)begin
	if(!rst)begin
		state <= S1;
	end
	else begin
		state <= nextstate;
	end
end

always@(*)begin
	case(state)
	S1 : begin
		nextstate = S2;
	end
	S2 : begin
		nextstate = S3;	
	end
	S3 : begin
		nextstate = S4;
	end
	S4 : begin
		nextstate = S1;
	end
	default:nextstate = S1;
	endcase
end

always@(posedge clk or negedge rst) begin
	if(!rst)begin
		clk_out <= 1'b0;
	end
	else if(nextstate==S2)begin
		clk_out <= 1'b1;
	end
	else begin
		clk_out <= 1'b0;
	end

end



endmodule