题解 | 非整数倍数据位宽转换24to128

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
    reg [3:0]   cnt;
    reg [127:0] data_locker;
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            cnt <= 4'd0;
        else if (valid_in)
            cnt <= cnt + 1;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            valid_out <= 1'b0;
        else if ((cnt==4'd5 || cnt==4'd10 || cnt==4'd15) && valid_in)
            valid_out <= 1'b1;
		else
		    valid_out <= 1'b0;
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_locker <= 0;
        else if (valid_in)
            data_locker <= {data_locker[103:0], data_in};
    end
    
    always@(posedge clk or negedge rst_n) begin
        if(~rst_n)
            data_out <= 0;
        else if(cnt==4'd5 && valid_in)
            data_out <= {data_locker[119:0], data_in[23:16]};
        else if(cnt==4'd10 && valid_in)
            data_out <= {data_locker[111:0], data_in[23: 8]};
        else if(cnt==4'd15 && valid_in)
            data_out <= {data_locker[103:0], data_in[23: 0]};
        else
            data_out <= data_out;
    end
endmodule

看題解才發現，原來直接把locker設定為120位寬會更好處理，只需要考慮差額，不用管locker的頭部了