题解 | 数据累加输出

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);

reg [2:0] cnt;

        always @(posedge clk or negedge rst_n)           
            begin                                        
                if(!rst_n)                               
                    cnt <= 3'd0;  
                else if(cnt == 3'd3 & valid_a & ready_a) //此處必須收發有效，因爲此時只讀了3個數據
                    cnt <= 3'd0; 
                else if(valid_a & ready_a)                               
                    cnt <= cnt + 1'b1;                  
            end

        assign ready_a = valid_b? (~ready_b?1'b0:1'b1): 1'b1;


        always @(posedge clk or negedge rst_n)           
            begin                                        
                if(!rst_n)                               
                    valid_b <= 1'b0;                                   
                else if(cnt == 3'd3 & valid_a & ready_a) //此處必須收發有效，容易漏掉                   
                    valid_b <= 1'b1; 
                else if(ready_b & valid_b)                                
                    valid_b <= 1'b0;               
            end 



        always @(posedge clk or negedge rst_n)           
            begin                                        
                if(!rst_n)                               
                    data_out <= 10'd0; 
                else if(ready_b & valid_a & ready_a & cnt == 3'd0)                                
                    data_out <= data_in;                                  
                else if(valid_a & ready_a)                                
                    data_out <= data_out + data_in;                                 
            end 


endmodule