题解 | 信号发生器

題解裏面看了好幾個，都遺漏了方波和鋸齒波為0時轉三角波的情況，用以下仿真代碼跑會出現wave到31的情況

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);


reg [5:0] cnt;
reg       rev;  
reg [1:0] wave_reg;  

always @(posedge clk or negedge rst_n)           
    begin                                     
        if(!rst_n) begin
            cnt<=6'd0;
        end else if(cnt == 6'd19) begin
            cnt<=6'd0;    
        end else if(wave_choise == 2'd0) begin
            cnt<=cnt + 1'b1;    
        end else begin
            cnt<=6'd0;
        end
    end

always @(posedge clk or negedge rst_n)           
    begin                                     
        if(!rst_n) begin
            rev<=1'b0;
        end else if(wave_choise == 2'd2 && wave == 5'd19) begin
            rev<=1'b0;    
        end else if(wave_choise == 2'd2 && wave == 5'd1) begin
            rev<=1'b1;        
        end else if(wave_choise == 2'd0 && cnt == 5'd19) begin
            rev<=1'b1;        
        end else if(wave_choise == 2'd0 && cnt != 5'd19) begin
            rev<=1'b0;        
        end else if(wave_choise == 2'd1 && wave == 5'd20) begin
            rev<=1'b1;        
        end else if(wave_choise == 2'd1 && wave != 5'd20) begin
            rev<=1'b0;        
        end
        
    end    

always @(posedge clk or negedge rst_n)           
    begin                                    
        if(!rst_n) begin                               
            wave <=5'd0;
        end else if(wave_choise == 2'd0) begin
            if (cnt == 6'd9) begin
                wave <=5'd20;
            end else if (cnt == 6'd19) begin
                wave <=5'd0;
            end                                
        end else if(wave_choise == 2'd1) begin
            if (wave == 5'd20) begin
                wave <=5'd0;
            end else begin
                wave <= wave + 1'b1; 
            end
        end else if(wave_choise == 2'd2) begin
                if (rev == 1'b1) begin
                    wave <= wave + 1'b1; 
                end else if (rev == 1'b0) begin
                    wave <= wave - 1'b1;
                end
            end                                                               
    end                                          
endmodule

或者這樣也可以吧

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);


reg [5:0] cnt;
reg       rev;  
reg [1:0] wave_reg;  

always @(posedge clk or negedge rst_n)           
    begin                                     
        if(!rst_n) begin
            cnt<=6'd0;
        end else if(cnt == 6'd19) begin
            cnt<=6'd0;    
        end else if(wave_choise == 2'd0) begin
            cnt<=cnt + 1'b1;    
        end else begin
            cnt<=6'd0;
        end
    end

always @(posedge clk or negedge rst_n)           
    begin                                     
        if(!rst_n) begin
            rev<=1'b0;
        end else if(wave_choise == 2'd2 && wave == 5'd20) begin
            rev<=1'b0;    
        end else if(wave_choise == 2'd2 && wave == 5'd0) begin
            rev<=1'b1;        
        end
        
    end    

always @(posedge clk or negedge rst_n)           
    begin                                    
        if(!rst_n) begin                               
            wave <=5'd0;
        end else if(wave_choise == 2'd0) begin
            if (cnt == 6'd9) begin
                wave <=5'd20;
            end else if (cnt == 6'd19) begin
                wave <=5'd0;
            end                                
        end else if(wave_choise == 2'd1) begin
            if (wave == 5'd20) begin
                wave <=5'd0;
            end else begin
                wave <= wave + 1'b1; 
            end
        end else if(wave_choise == 2'd2) begin
                if (rev == 1'b1) begin
                    if (wave == 5'd20) begin
                        wave <= wave - 1'b1; 
                    end else begin
                        wave <= wave + 1'b1;   
                    end

                end else if (rev == 1'b0) begin
                    if (wave == 5'd0) begin
                        wave <= wave + 1'b1; 
                    end else begin
                        wave <= wave - 1'b1;   
                    end
                end
            end                                                               
    end                                          
endmodule

`timescale 1ns/1ns

module test_tb;

    reg clk;
    reg rst_n;
    reg [1:0] wave_choise;
    wire [4:0]wave;


    // 实例化被测试模块
    signal_generator uut (
        .clk(clk),
        .rst_n(rst_n),
        .wave_choise(wave_choise),
        .wave(wave)
    );

    // 生成时钟信号
    initial begin
        clk = 0;
        forever #5 clk = ~clk;  // 10ns 周期的时钟
    end

    // 测试过程
    initial begin
        // 初始化
        rst_n = 0;
        wave_choise = 0;
        #20;
        rst_n = 1; 
        #200
        
        wave_choise = 1; #200
        wave_choise = 2; #400
        wave_choise = 0; #200
        wave_choise = 2; #400       
        wave_choise = 1; #200
        wave_choise = 0; #100       
        
        wave_choise = 1; #100
        wave_choise = 2; #200
        wave_choise = 0; #100
        wave_choise = 2; #200       
        wave_choise = 1; #100
        wave_choise = 0; #150
        
        wave_choise = 1; #150
        wave_choise = 2; #150
        wave_choise = 0; #150
        wave_choise = 2; #150       
        wave_choise = 1; #150
        wave_choise = 0;         
        // 结束仿真
         #150 $finish;
    end



endmodule