题解 | #4bit超前进位加法器电路#

`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

	wire [3:0] C;
	assign C[0] =  (A_in[0] & B_in[0]) || (A_in[0] ^ B_in[0])&C_1;
	assign S[0] = A_in[0] ^ B_in[0] ^ C_1;
	assign CO = C[3];
    genvar k;
    for( k=1; k<4; k=k+1) begin
		assign C[k] = (A_in[k] & B_in[k]) || (A_in[k] ^ B_in[k])&C[k-1];
        assign S[k] = A_in[k] ^ B_in[k] ^ C[k-1];
    end
endmodule