题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input wire clk,
input wire rst,
input wire [15:0]d,
input wire [1:0]sel,

output reg [4:0]out,
output reg validout
);
reg [15:0]locked_d;
//*************code***********//
always@(posedge clk or negedge rst)begin
    if(~rst)begin
        out <= 5'd0;
        validout <= 1'd0;
    end
    else begin
        case(sel)
        2'd0:begin
            validout <= 0;
            locked_d <= d;
            out <= 0;
        end
        2'd1:begin
            validout <= 1;
            out[4:0] <= {1'b0,locked_d[3:0]}+{1'b0,locked_d[7:4]};
        end
        2'd2:begin
            validout <= 1;
            out[4:0] <= {1'b0,locked_d[3:0]}+{1'b0,locked_d[11:8]};
        end
        2'd3:begin
            validout <= 1;
            out[4:0] <= {1'b0,locked_d[3:0]}+{1'b0,locked_d[15:12]};
        end
        endcase
    end
end

//*************code***********//
endmodule