题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg [7:0] mid_d;
reg [1:0] cyc;
always @(posedge clk or negedge rst)begin
    if (rst == 0)begin
        mid_d <= 0;
        cyc <= 0;
        input_grant <= 0;
    end
    else 
        if(cyc == 0)begin
            cyc <= cyc+1;
            mid_d <= d;
            input_grant <= 1;
        end
        else begin
            cyc <= cyc+1;
            input_grant <= 0;
        end
end

always @(posedge clk or negedge rst)begin
    if (rst == 0)
        out <= 0;
    else 
        case(cyc)
        2'b00: out <= d;
        2'b01: out <= mid_d*3;
        2'b10: out <= mid_d*7;
        2'b11: out <= mid_d*8;
        endcase
end



//*************code***********//
endmodule