题解 | #信号顺序调整#

`timescale 1ns/1ns

module top_module(
    input [15:0] in,
    output [15:0] out
);

wire [3:0] a,b,c,d;
assign a = in[3:0];
assign b = in[7:4];
assign c = in[11:8];
assign d = in[15:12];
assign out = {d,c,b,a};


endmodule