题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);

	localparam WIDTH_IN = 8;
	localparam WIDTH_OUT = 12;
	reg [WIDTH_IN+WIDTH_OUT-1:0] buff;
	integer i;
	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			buff <= 0;
		end else begin
			if (valid_in) begin
				buff[WIDTH_IN-1:0] <= data_in;
				for (i = 1; i < 6; i ++) begin
					buff[(i+1)*WIDTH_IN-1-:WIDTH_IN] <= buff[(i)*WIDTH_IN-1-:WIDTH_IN];
				end
			end else begin
				buff <= buff;
			end
		end
	end
	
	reg [$clog2(WIDTH_IN+WIDTH_OUT)-1:0] num;
	always @(posedge clk or negedge rst_n) begin
		if (~rst_n) begin
			num <= 0;
		end else begin
			if (valid_in & ~valid_out) begin
				num <= num + WIDTH_IN;
			end else if (~valid_in & valid_out) begin
				num <= num - WIDTH_OUT;
			end else if (valid_in & valid_out) begin
				num <= num + WIDTH_IN - WIDTH_OUT;
			end else begin
				num <= num;
			end
		end
	end
				
	always @* begin
		if (~rst_n) begin
			valid_out = 0;
			data_out = 0;
		end else begin
			if (num >= WIDTH_OUT) begin
				valid_out = 1;
				data_out = buff[num-1-:WIDTH_OUT];
			end else begin
				valid_out = 0;
				data_out = data_out;
			end
		end
	end

endmodule

参数化设计，适用于输入位宽小于输出位宽的所有情形。