题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;

reg [1:0] cur_state , next_state;

always @(posedge clk or negedge rst) begin
	if (!rst)
		cur_state <= S0;
	else 
		cur_state <= next_state;    
end

always @(*) begin
	case (cur_state) 
		S0 :	next_state = data ? S1 : S0;
		S1 : 	next_state = data ? S2 : S1;
		S2 : 	next_state = data ? S3 : S2;
		S3 : 	next_state = data ? S0 : S3;
	endcase
end
     
always @(posedge clk or negedge rst) begin
	if(!rst) begin
		flag <= 0;
	end else begin
		if(cur_state == S3 && next_state == S0) 
			flag <= 1;
		else 
			flag <= 0;
	end 
end
//*************code***********//
endmodule