题解 | #时钟分频（偶数）#

`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
// reg [2:0] cnt;


// always@(posedge clk_in or negedge rst)
//     if(!rst)
//         cnt <= 3'b111;
//     else
//         cnt <= cnt + 1'b1;
    
// assign clk_out2 = ~cnt[0];
// assign clk_out4 = ~cnt[1];
// assign clk_out8 = ~cnt[2];

//*************code***********//


reg clk_out2_reg;
reg clk_out8_rag;
reg clk_out4_rag;

reg                 [1:0]            cnt_4;
reg                 [1:0]            cnt_8;


always @(posedge clk_in or negedge rst) begin
    if (!rst) begin
        clk_out2_reg <= 1'b0;
    end
    else
        clk_out2_reg <= ~clk_out2_reg;
end


always @(posedge clk_in or negedge rst) begin
if (!rst) begin
        cnt_4 <= 2'd0;
    end
    else if (cnt_4 >= 2'd1) begin
        cnt_4 <= 2'd0;
    end
    else
        cnt_4 <= cnt_4 + 1'b1;
end



always @(posedge clk_in or negedge rst) begin
    if (!rst) begin
        cnt_8 <= 2'd0;
    end
    else if (cnt_8 >= 2'd3) begin
        cnt_8 <= 2'd0;
    end
    else
        cnt_8 <= cnt_8 + 1'b1;
end




always@(posedge clk_in or negedge rst)begin
    if (!rst) begin
        clk_out4_rag <= 1'b0;
    end
    else if (cnt_4 == 2'd0) begin
        clk_out4_rag <= ~clk_out4_rag;
    end
    else
        clk_out4_rag <= clk_out4_rag;
end




always@(posedge clk_in or negedge rst)begin
    if (!rst) begin
        clk_out8_rag <= 1'b0;
    end
    else if (cnt_8 == 2'd0) begin
        clk_out8_rag <= ~clk_out8_rag;
    end
    else
        clk_out8_rag <= clk_out8_rag;
end

assign clk_out2 = clk_out2_reg;
assign clk_out4 = clk_out4_rag;
assign clk_out8 = clk_out8_rag;
endmodule