题解 | #数据串转并电路#

`timescale 1ns/1ps
module testbench_top();
	
////////////////////////////////////////////////////////////
//设置时钟周期
`define CLK_PERIOD_100M 10	

//定义参数


////////////////////////////////////////////////////////////
//声明接口
reg clk;
reg rst_n;
reg valid_a;
reg data_a;

wire ready_a;
wire valid_b;
wire 	[5:0]	data_b;
////////////////////////////////////////////////////////////	
//例化待测试模块
	s_to_p_a inst_s_to_p
		(
			.clk     (clk),
			.rst_n   (rst_n),
			.valid_a (valid_a),
			.data_a  (data_a),
			.ready_a (ready_a),
			.valid_b (valid_b),
			.data_b  (data_b)
		);
	

////////////////////////////////////////////////////////////
//产生复位和时钟
	//对复位和时钟进行初始化
initial begin
	clk <= 0;
	rst_n <= 0;
	#1000;
	rst_n <= 1;
end

	//产生时钟
always #(`CLK_PERIOD_100M/2) clk = ~clk;
////////////////////////////////////////////////////////////
//定义二维数组

//读取文本文件到二维数组


////////////////////////////////////////////////////////////
//产生测试激励信号
initial begin
	valid_a <= 0;
	data_a <= 0;
	#2
	@(posedge rst_n);
	@(posedge clk);
	gen_data101010();
	@(posedge clk);
	gen_data111000();
	@(posedge clk);
	gen_data000111();
	gen_data101010();
	gen_data111000();
	#1000;
	// $fclose("file_goden");
	// $fclose("file_test");
	$finish;	
end

//定义task
task gen_data101010;
	begin
		valid_a <= 1;
		data_a <= 1;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		valid_a <= 0;
	end
endtask

task gen_data111000;
	begin
		valid_a <= 1;
		data_a <= 1;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		valid_a <= 0;
	end
endtask

task gen_data000111;
	begin
		valid_a <= 1;
		data_a <= 0;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 0;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		data_a <= 1;
		@(posedge clk);
		valid_a <= 0;
	end
endtask
////////////////////////////////////////////////////////////
//打开文件
integer file_goden,file_test;
initial file_goden = $fopen("./output_file/file_goden.txt","w");
initial file_test = $fopen("./output_file/file_test.txt","w");
////////////////////////////////////////////////////////////
//写入数据
always@(posedge clk) begin
	if(valid_a)								$fwrite(file_goden,"%b\n",data_a);
end

always@(posedge clk) begin
	if(valid_b)begin
		$fwrite(file_test,"%b\n",data_b[5]);
		$fwrite(file_test,"%b\n",data_b[4]);
		$fwrite(file_test,"%b\n",data_b[3]);
		$fwrite(file_test,"%b\n",data_b[2]);
		$fwrite(file_test,"%b\n",data_b[1]);
		$fwrite(file_test,"%b\n",data_b[0]);
	end								
end


////////////////////////////////////////////////////////////
//对比数据打印结果
initial begin
	$dumpfile("out.vcd");
	$dumpvars(0,testbench_top);
end

endmodule