题解 | #状态机-重叠序列检测#

`timescale 1ns/1ns

module sequence_test2(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//
//采用摩尔型状态机状态机 输出只和状态有关 这时就能方便检测重叠序列。 上一题可以采用米勒型状态机
reg [4:0] cur_state   ;
reg [4:0] nex_state   ;

localparam  S0 =  5'b00001    ,
            S1 =  5'b00010    ,
			S2 =  5'b00100    ,
			S3 =  5'b01000    ,
			S4 =  5'b10000    ;


always@(posedge clk or negedge rst)begin
    if(!rst)
	    cur_state <= S0           ;
	else 
	    cur_state <= nex_state    ;
end

always@(*)begin
	case(cur_state)
	    S0 : nex_state =  (data == 1)? S1 : S0  ;
		S1 : nex_state =  (data == 0)? S2 : S1  ;
		S2 : nex_state =  (data == 1)? S3 : S0  ;
		S3 : nex_state =  (data == 1)? S4 : S2  ;
		S4 : nex_state =  (data == 1)? S1 : S2  ;
		default : nex_state = S0                ;
	endcase
end

always@(posedge clk or negedge rst)begin
    if(!rst)
	    flag <= 1'b0               ;     
	else begin
	    case(cur_state)
		    S4:     flag <=  1'b1   ;
			default:flag <= 1'b0    ;
		endcase    
	end
	    
end
//*************code***********//
endmodule