题解 | #非整数倍数据位宽转换8to12#（精华题解）

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);

//此题与上一题的思路是一致的，只是说 这一道题 只需要缓存上一个时钟周期的值就行
reg  [1:0]  COUNT          ;
reg  [7:0] data_in_reg     ;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        COUNT <= 'd0              ;
    else if(COUNT == 'd2 && valid_in == 1'b1)
	    COUNT <= 'd0              ;  
	else if(valid_in == 1'b1)
	    COUNT <= COUNT + 1'b1   ; 
end


always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        data_in_reg <= 'd0                            ;
    else if(valid_in == 1'b1)
	    data_in_reg <= data_in                        ;   
end


always@(posedge clk or negedge rst_n)begin
    if(!rst_n)begin
        valid_out <= 1'b0                                    ;
		data_out  <=  'd0                                   ;
	end
    else if(COUNT == 'd1  && valid_in == 1'b1)begin
       valid_out <= 1'b1                                    ;
	   data_out  <=  {data_in_reg,data_in[7:4]}             ;
	end
	else if(COUNT == 'd2 && valid_in == 1'b1)begin
       valid_out <= 1'b1                                    ;
	   data_out  <=  {data_in_reg[3:0],data_in}             ;
	end
	else begin
	   valid_out <= 1'b0                                     ;
	   data_out  <= data_out                                 ;
	end
end

endmodule