题解 | #可置位计数器#

`timescale 1ns/1ns

module count_module(
	input clk,
	input rst_n,
	input set,
	input [3:0] set_num,

	output reg [3:0]number,
	output reg zero
);

reg [3:0]num_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    num_reg <= 4'b0;
	else if (num_reg == 4'd15)
	    num_reg <= 4'b0;
	else if (set == 1'b1)
	    num_reg <= set_num;
	else 
	    num_reg <= num_reg + 1'b1;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    number <= 4'b0;
	else 
	    number <= num_reg;

always@(posedge clk or negedge rst_n)
    if (rst_n == 1'b0)
	    zero <= 1'b0;
	else if (num_reg == 4'd0)
	    zero <= 1'b1;
	else 
	    zero <= 1'b0;

endmodule

题中给出的计数器信号为啥要再打一拍啊，感觉有顶啊不合乎常理。