题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//

reg [15:0] in_reg;
reg [4:0] out_reg;

// 有效数据保持
always@(posedge clk or negedge rst)
    if(!rst)
        in_reg <= 5'd0;
    else if(sel == 2'b00)
        in_reg <= d;
    else
        in_reg <= in_reg;

//out 信号产生
always@(posedge clk or negedge rst)
    if(!rst)
        out_reg <= 5'd0;
    else begin
        case(sel)
            2'd0 : out_reg <= 5'd0;
            2'd1:out_reg <= in_reg[3:0]+ in_reg[7:4];
            2'd2:out_reg <= in_reg[3:0]+in_reg[11:8];
            2'd3:out_reg <= in_reg[3:0]+in_reg[15:12];
            default : out_reg <= 5'd0;
        endcase
    end

//输出信号
assign out = out_reg;

//validout信号产生
assign validout = |sel;

//*************code***********//
endmodule