题解 | #信号发生器#

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
reg [4:0] cnt0;
reg dec;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
	wave <= 'd0;
	cnt0 <= 'd0;
	dec  <= 'd1;
	end
	else 
	case(wave_choise)
	0: begin
		wave <= (cnt0 == 5'd19) ? 0:
				(cnt0 == 5'd9)  ? 5'd20:wave;
		cnt0 <= (cnt0 == 5'd19) ?'d0 :(cnt0 + 1) ;
		dec  <= 'd1;
	end
	1: begin
		wave <= (wave < 5'd20) ?(wave + 1) : 'd0;
		dec  <= 'd1;
	end
	2:begin
		wave <= (dec && (wave!='d0))?(wave -1):
				(!dec && (wave =='d20))?wave-1:wave+1;
		dec  <= (wave=='d0 || wave=='d20) ? ~dec:dec;
	end
	default:begin
		wave <= 'd0;
		cnt0 <= 'd0;
		dec  <= 'd1;
	end
	endcase
end

endmodule